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Re: [PATCH] Don't use SSE4_2 instructions on Intel Silvermont Micro Architecture.
- From: Dmitrieva Liubov <liubov dot dmitrieva at gmail dot com>
- To: Ondřej Bílka <neleai at seznam dot cz>
- Cc: libc-alpha at sourceware dot org
- Date: Mon, 17 Jun 2013 21:56:10 +0400
- Subject: Re: [PATCH] Don't use SSE4_2 instructions on Intel Silvermont Micro Architecture.
- References: <CAHjhQ93=uegeZg9iTqoJ+PFuUrvn8e2mA8tZ96Jy4CaV6aPbWg at mail dot gmail dot com> <20130617163729 dot GA15981 at domone dot kolej dot mff dot cuni dot cz>
I checked that functions.
In case of strspn/strcspn/strpbrk to switch SSE4_2 off is bad because
there are no optimized sse2 versions to call instead.
Default versions are not sse there.
So, it seems we need to create a new flag for Silvermont like
"slowPcmpistri" and fix switches in functions where optimized sse2
exist.
Or implement optimized sse2 strspn/strcspn/strpbrk and switch SSE4_2 completely.
--
Liubov Dmitrieva
Intel Corporation
On Mon, Jun 17, 2013 at 8:37 PM, OndÅej BÃlka <neleai@seznam.cz> wrote:
> On Mon, Jun 17, 2013 at 07:14:31PM +0400, Dmitrieva Liubov wrote:
>> The second patch for Silvermont we hope to have in 2.18.
>>
>> SSE4_2 instructions can be executed on Silvermont, so some string
>> functions like strchr where sse4_2 version is available were switched
>> to sse4_2 versions. But it produces huge regressions.
>>
>> It would be good to switch SSE4_2 bit off.
>>
>> Tested on my machine.
>> Ok to commit?
>>
> Not yet.
>
> There are strspn/strcspn/strpbrk which where SSE4_2 gives big boost.
> If they also have regression then I am ok with this patch. Otherwise I
> would look how change ifunc of strspn et al.