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PATCH: Enable 32-bit SSE4.2 strcasecmp/strncasecmp for libc.a
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: GNU C Library <libc-alpha at sourceware dot org>
- Date: Mon, 1 Jul 2013 13:55:26 -0700
- Subject: PATCH: Enable 32-bit SSE4.2 strcasecmp/strncasecmp for libc.a
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
Hi,
When 32-bit SSE4.2 strcasecmp/strncasecmp was added to glibc by commit:
http://sourceware.org/git/?p=glibc.git;a=commitdiff;h=6abf346582ba678f4850a88b4a5950593841df1d
it failed to properly enable 32-bit SSE4.2 strcasecmp/strncasecmp for
libc.a. This patch enable 32-bit SSE4.2 strcasecmp/strncasecmp in
libc.a. Tested on Intel Core i7. OK to install?
Thanks.
H.J.
----
diff --git a/ChangeLog b/ChangeLog
index 406ca28..0a226d3 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2013-07-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * sysdeps/i386/i686/multiarch/strcasecmp.S (__strcasecmp): Enable
+ SSE4.2 strcasecmp for libc.a.
+ * sysdeps/i386/i686/multiarch/strncase.S (__strncasecmp): Likewise.
+
2013-06-28 Liubov Dmitrieva <liubov.dmitrieva@intel.com>
* sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): Set
diff --git a/sysdeps/i386/i686/multiarch/strcasecmp.S b/sysdeps/i386/i686/multiarch/strcasecmp.S
index 3b38214..2444af2 100644
--- a/sysdeps/i386/i686/multiarch/strcasecmp.S
+++ b/sysdeps/i386/i686/multiarch/strcasecmp.S
@@ -54,12 +54,9 @@ ENTRY(__strcasecmp)
testl $bit_SSSE3, CPUID_OFFSET+index_SSSE3+__cpu_features
jz 2f
leal __strcasecmp_ssse3, %eax
-#if 0
- // XXX Temporarily
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
leal __strcasecmp_sse4_2, %eax
-#endif
2: ret
END(__strcasecmp)
#endif
diff --git a/sysdeps/i386/i686/multiarch/strncase.S b/sysdeps/i386/i686/multiarch/strncase.S
index 51c6d72..939cd96 100644
--- a/sysdeps/i386/i686/multiarch/strncase.S
+++ b/sysdeps/i386/i686/multiarch/strncase.S
@@ -54,12 +54,9 @@ ENTRY(__strncasecmp)
testl $bit_SSSE3, CPUID_OFFSET+index_SSSE3+__cpu_features
jz 2f
leal __strncasecmp_ssse3, %eax
-#if 0
- // XXX Temporarily
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
leal __strncasecmp_sse4_2, %eax
-#endif
2: ret
END(__strncasecmp)
#endif