This is the mail archive of the libc-hacker@sources.redhat.com mailing list for the glibc project.
Note that libc-hacker is a closed list. You may look at the archives of this list, but subscription and posting are not open.
| Index Nav: | [Date Index] [Subject Index] [Author Index] [Thread Index] | |
|---|---|---|
| Message Nav: | [Date Prev] [Date Next] | [Thread Prev] [Thread Next] |
The ia64 fenv functions seem wrong to me. Here is a patch. With this patch,
I got only
make[2]: *** [/home/work/build/glibc/math/test-float.out] Error 1
make[2]: *** [/home/work/build/glibc/math/test-double.out] Error 1
make[2]: *** [/home/work/build/glibc/math/test-ldouble.out] Error 134
make[2]: *** [/home/work/build/glibc/math/test-ildoubl.out] Error 134
make[2]: *** [/home/work/build/glibc/math/test-ifloat.out] Error 1
make[2]: *** [/home/work/build/glibc/math/test-idouble.out] Error 1
in "make check".
Thanks.
H.J.
----
2000-09-20 H.J. Lu <hjl@gnu.org>
* sysdeps/ia64/fpu/fclrexcpt.c (feclearexcept): Use fexcept_t
instead of fenv_t.
* sysdeps/ia64/fpu/fedisblxcpt.c (fedisableexcept): Fix the logic.
* sysdeps/ia64/fpu/feenablxcpt.c (feenableexcept): Likewise.
* sysdeps/ia64/fpu/fegetexcept.c (fegetexcept): Likewise.
* sysdeps/ia64/fpu/fgetexcptflg.c (fegetexceptflag): Likewise.
* sysdeps/ia64/fpu/fsetexcptflg.c (fesetexceptflag): Likewise.
* sysdeps/ia64/fpu/fesetenv.c (fesetenv): Use fenv_t instead of
unsigned long int.
* sysdeps/ia64/fpu/fesetround.c (fesetround): Likewise.
Index: sysdeps/ia64/fpu/fclrexcpt.c
===================================================================
RCS file: /work/cvs/gnu/glibc/sysdeps/ia64/fpu/fclrexcpt.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 fclrexcpt.c
--- sysdeps/ia64/fpu/fclrexcpt.c 2000/05/21 21:12:03 1.1.1.1
+++ sysdeps/ia64/fpu/fclrexcpt.c 2000/09/21 01:51:20
@@ -24,13 +24,13 @@
int
feclearexcept (int excepts)
{
- fenv_t fpsr;
+ fexcept_t fpsr;
/* Get the current state. */
__asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (fpsr));
/* Clear the relevant bits. */
- fpsr &= ~(((unsigned long int) ((excepts & FE_ALL_EXCEPT) << 13)));
+ fpsr &= ~(((fexcept_t) ((excepts & FE_ALL_EXCEPT) << 13)));
/* Put the new state in effect. */
__asm__ __volatile__ ("mov.m ar.fpsr=%0" :: "r" (fpsr) : "memory");
Index: sysdeps/ia64/fpu/fedisblxcpt.c
===================================================================
RCS file: /work/cvs/gnu/glibc/sysdeps/ia64/fpu/fedisblxcpt.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 fedisblxcpt.c
--- sysdeps/ia64/fpu/fedisblxcpt.c 2000/05/21 21:12:03 1.1.1.1
+++ sysdeps/ia64/fpu/fedisblxcpt.c 2000/09/21 01:23:01
@@ -27,11 +27,13 @@ fedisableexcept (int excepts)
fenv_t new_fpsr;
/* Get the current fpsr. */
- __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (old_fpsr));
+ __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (new_fpsr));
- new_fpsr = old_fpsr |= FE_ALL_EXCEPT;
+ excepts &= FE_ALL_EXCEPT;
+ old_fpsr = (~new_fpsr) & FE_ALL_EXCEPT;
+ new_fpsr |= (fenv_t) excepts;
__asm__ __volatile__ ("mov.m ar.fpsr=%0" :: "r" (new_fpsr) : "memory");
- return (old_fpsr ^ FE_ALL_EXCEPT) & FE_ALL_EXCEPT;
+ return old_fpsr;
}
Index: sysdeps/ia64/fpu/feenablxcpt.c
===================================================================
RCS file: /work/cvs/gnu/glibc/sysdeps/ia64/fpu/feenablxcpt.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 feenablxcpt.c
--- sysdeps/ia64/fpu/feenablxcpt.c 2000/05/21 21:12:03 1.1.1.1
+++ sysdeps/ia64/fpu/feenablxcpt.c 2000/09/21 01:21:48
@@ -27,12 +27,13 @@ feenableexcept (int excepts)
fenv_t new_fpsr;
/* Get the current fpsr. */
- __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r " (old_fpsr));
+ __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r " (new_fpsr));
- new_fpsr = ((old_fpsr & FE_ALL_EXCEPT)
- | (old_fpsr & ((unsigned long int) excepts ^ FE_ALL_EXCEPT)));
+ excepts &= FE_ALL_EXCEPT;
+ old_fpsr = (~new_fpsr) & FE_ALL_EXCEPT;
+ new_fpsr &= ~((fenv_t) excepts);
__asm__ __volatile__ ("mov.m ar.fpsr=%0" :: "r" (new_fpsr) : "memory");
- return (old_fpsr ^ FE_ALL_EXCEPT) & FE_ALL_EXCEPT;
+ return old_fpsr;
}
Index: sysdeps/ia64/fpu/fegetexcept.c
===================================================================
RCS file: /work/cvs/gnu/glibc/sysdeps/ia64/fpu/fegetexcept.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 fegetexcept.c
--- sysdeps/ia64/fpu/fegetexcept.c 2000/05/21 21:12:03 1.1.1.1
+++ sysdeps/ia64/fpu/fegetexcept.c 2000/09/21 01:27:21
@@ -27,5 +27,5 @@ fegetexcept (void)
__asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (fpsr));
- return (fpsr ^ FE_ALL_EXCEPT) & FE_ALL_EXCEPT;
+ return (~fpsr) & FE_ALL_EXCEPT;
}
Index: sysdeps/ia64/fpu/fesetenv.c
===================================================================
RCS file: /work/cvs/gnu/glibc/sysdeps/ia64/fpu/fesetenv.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 fesetenv.c
--- sysdeps/ia64/fpu/fesetenv.c 2000/05/21 21:12:03 1.1.1.1
+++ sysdeps/ia64/fpu/fesetenv.c 2000/09/21 01:28:22
@@ -30,8 +30,8 @@ fesetenv (const fenv_t *envp)
Magic encoding of default values: bit 62+63 set (which will never
happen for a user-space address) means it's not indirect.
*/
- if (((unsigned long int) envp >> 62) == 0x03)
- env = (unsigned long int) envp & 0x3fffffffffffffff;
+ if (((fenv_t) envp >> 62) == 0x03)
+ env = (fenv_t) envp & 0x3fffffffffffffff;
else
env = *envp;
Index: sysdeps/ia64/fpu/fesetround.c
===================================================================
RCS file: /work/cvs/gnu/glibc/sysdeps/ia64/fpu/fesetround.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 fesetround.c
--- sysdeps/ia64/fpu/fesetround.c 2000/05/21 21:12:03 1.1.1.1
+++ sysdeps/ia64/fpu/fesetround.c 2000/09/21 01:29:11
@@ -23,7 +23,7 @@
int
fesetround (int round)
{
- unsigned long int fpsr;
+ fenv_t fpsr;
if (round & ~3)
return 0;
@@ -32,7 +32,7 @@ fesetround (int round)
__asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (fpsr));
/* Set the relevant bits. */
- fpsr = (fpsr & ~(3UL << 10)) | ((unsigned long int) round << 10);
+ fpsr = (fpsr & ~(3UL << 10)) | ((fenv_t) round << 10);
/* Put the new state in effect. */
__asm__ __volatile__ ("mov.m ar.fpsr=%0" :: "r" (fpsr) : "memory");
Index: sysdeps/ia64/fpu/fgetexcptflg.c
===================================================================
RCS file: /work/cvs/gnu/glibc/sysdeps/ia64/fpu/fgetexcptflg.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 fgetexcptflg.c
--- sysdeps/ia64/fpu/fgetexcptflg.c 2000/05/21 21:12:03 1.1.1.1
+++ sysdeps/ia64/fpu/fgetexcptflg.c 2000/09/21 01:52:14
@@ -23,12 +23,12 @@
int
fegetexceptflag (fexcept_t *flagp, int excepts)
{
- fenv_t fpsr;
+ fexcept_t fpsr;
/* Get the current exceptions. */
__asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (fpsr));
- *flagp = (fpsr ^ FE_ALL_EXCEPT) & excepts & FE_ALL_EXCEPT;
+ *flagp = (fpsr >> 13) & excepts & FE_ALL_EXCEPT;
/* Success. */
return 0;
Index: sysdeps/ia64/fpu/fsetexcptflg.c
===================================================================
RCS file: /work/cvs/gnu/glibc/sysdeps/ia64/fpu/fsetexcptflg.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 fsetexcptflg.c
--- sysdeps/ia64/fpu/fsetexcptflg.c 2000/05/21 21:12:03 1.1.1.1
+++ sysdeps/ia64/fpu/fsetexcptflg.c 2000/09/21 01:57:25
@@ -31,10 +31,10 @@ fesetexceptflag (const fexcept_t *flagp,
/* Get the reverse bits so we can enable the exceptions flagged
rather than disable them. */
- excepts ^= FE_ALL_EXCEPT;
+ fpsr &= ~(excepts & FE_ALL_EXCEPT);
/* Set all the bits that were called for. */
- fpsr = (fpsr & ~FE_ALL_EXCEPT) | (*flagp & excepts & FE_ALL_EXCEPT);
+ fpsr |= *flagp & excepts & FE_ALL_EXCEPT;
/* And store it back. */
__asm__ __volatile__ ("mov.m ar.fpsr=%0" :: "r" (fpsr) : "memory");
| Index Nav: | [Date Index] [Subject Index] [Author Index] [Thread Index] | |
|---|---|---|
| Message Nav: | [Date Prev] [Date Next] | [Thread Prev] [Thread Next] |