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Re: arm-elf thumb-2 issue in newlib or gas?
Hi Andreas,
Darn - OK, changing the assembler is easy, but I have no idea how the
new ARMv7 special purpose registers (and stacks) should be initialized.
Do you know ? If not then we can just suppress the offending code for
__thumb2__, but that is far from ideal.
Unfortunately not, we've just started to look at cortex-m3.
OK, well the crt0.S will work if used in User mode, so I am going to
check in these patches for now. At some point in the future I will look
at how we should be initializing the interrupt stack pointers.
Cheers
Nick
newlib/ChangeLog
2008-04-25 Nick Clifton <nickc@redhat.com>
* libc/machine/arm/setjmp.S: Fix thumb2 support.
libgloss/ChangeLog
2008-04-25 Nick Clifton <nickc@redhat.com>
* arm/crt0.S: Allow assembly under ARMv7 ISA. Support for
initializing stack pointers for interrupt modes is still pending.
Index: newlib/libc/machine/arm/setjmp.S
===================================================================
RCS file: /cvs/src/src/newlib/libc/machine/arm/setjmp.S,v
retrieving revision 1.2
diff -c -3 -p -r1.2 setjmp.S
*** newlib/libc/machine/arm/setjmp.S 7 Feb 2006 18:44:54 -0000 1.2
--- newlib/libc/machine/arm/setjmp.S 25 Apr 2008 08:57:27 -0000
*************** SYM (\name):
*** 120,126 ****
--- 120,131 ----
FUNC_START setjmp
/* Save all the callee-preserved registers into the jump buffer. */
+ #ifdef __thumb2__
+ stmea a1!, { v1-v7, fp, ip, lr }
+ str sp, [a1],#+4
+ #else
stmea a1!, { v1-v7, fp, ip, sp, lr }
+ #endif
#if 0 /* Simulator does not cope with FP instructions yet. */
#ifndef __SOFTFP__
*************** SYM (\name):
*** 142,148 ****
--- 147,158 ----
/* If we have stack extension code it ought to be handled here. */
/* Restore the registers, retrieving the state when setjmp() was called. */
+ #ifdef __thumb2__
+ ldmfd a1!, { v1-v7, fp, ip, lr }
+ ldr sp, [a1],#+4
+ #else
ldmfd a1!, { v1-v7, fp, ip, sp, lr }
+ #endif
#if 0 /* Simulator does not cope with FP instructions yet. */
#ifndef __SOFTFP__
Index: libgloss/arm/crt0.S
===================================================================
RCS file: /cvs/src/src/libgloss/arm/crt0.S,v
retrieving revision 1.6
diff -c -3 -p -r1.6 crt0.S
*** libgloss/arm/crt0.S 13 Aug 2007 18:13:39 -0000 1.6
--- libgloss/arm/crt0.S 25 Apr 2008 08:57:27 -0000
***************
*** 82,93 ****
--- 82,99 ----
ldr r3, .Lstack
cmp r3, #0
+ #ifdef __thumb2__
+ it eq
+ #endif
ldreq r3, .LC0
/* Note: This 'mov' is essential when starting in User, and ensures we
always get *some* sp value for the initial mode, even if we
have somehow missed it below (in which case it gets the same
value as FIQ - not ideal, but better than nothing.) */
mov sp, r3
+ #ifdef __thumb2__
+ /* XXX Fill in stack assignments for interrupt modes. */
+ #else
mrs r2, CPSR
tst r2, #0x0F /* Test mode bits - in User of all are 0 */
beq .LC23 /* "eq" means r2 AND #0x0F is 0 */
***************
*** 109,114 ****
--- 115,121 ----
sub r3, r3, #0x2000
msr CPSR_c, #0xD3 /* Supervisory mode, interrupts disabled */
+
mov sp, r3
sub r3, r3, #0x8000 /* Min size 32k */
bic r3, r3, #0x00FF /* Align with current 64k block */
***************
*** 116,124 ****
str r3, [r3, #-4] /* Move value into user mode sp without */
ldmdb r3, {sp}^ /* changing modes, via '^' form of ldm */
-
orr r2, r2, #0xC0 /* Back to original mode, presumably SVC, */
msr CPSR_c, r2 /* with FIQ/IRQ disable bits forced to 1 */
.LC23:
/* Setup a default stack-limit in-case the code has been
compiled with "-mapcs-stack-check". Hard-wiring this value
--- 123,131 ----
str r3, [r3, #-4] /* Move value into user mode sp without */
ldmdb r3, {sp}^ /* changing modes, via '^' form of ldm */
orr r2, r2, #0xC0 /* Back to original mode, presumably SVC, */
msr CPSR_c, r2 /* with FIQ/IRQ disable bits forced to 1 */
+ #endif
.LC23:
/* Setup a default stack-limit in-case the code has been
compiled with "-mapcs-stack-check". Hard-wiring this value