Re: corrected: tapset/script information template

[William Cohen <wcohen at redhat dot com>]

Ananth N Mavinakayanahalli wrote:
> Vara Prasad wrote:
>
> > Hi Will,
> >
> > Thanks for taking care of this.  This is an excellent start for 
> > function tracing.
> > I am sure this feature will make many kernel developers happy.
> >
> > Ananth, can you check to see if this approach works on PPC platform.
>
> PowerPC (POWER4 and above) have hardware support only for data address
> breakproints (they have one Data Address Breakpoint Register - DABR). If
> we are talking of using debug hadware to track text addresses, then, no
> PPC doesn't provide a facility for us to use.
>
> IIUC, the PPC designers discontinued IABR (Instruction Address
> Breakpoint Register) since they thought all breakpoints on a text 
> address can be handled in software.
>
> Thanks,
> Ananth

The 970FX manual mentions the IABR.

However, I was thinking about using branch trace mode. I am looking at 
page 116 of the 970FX_user_manual_v1.14.pdf. The Machine State Register 
(MSR) has bit 54 which appear to cause a trap for each branch. The main 
difficulty I see with PPC is distiguishing between a branch and return. 
Using this would allow tracing a particular thread. It won't be cheap 
for the tread being traced, but it won't incurr overhead on the threads 
not being traced.

What approaches for handling breakpoints on text address were suggested? 
Replacing the instruction at that location with a software break point? 
That would be triggered on threads that encountered that location. The 
dynamic rewrite of the code?

-Will