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[PATCH] Build the RISC-V texinfo documentation
- From: Palmer Dabbelt <palmer at dabbelt dot com>
- To: binutils at sourceware dot org
- To: joseph at codesourcery dot com
- Cc: Andrew Waterman <andrew at sifive dot com>
- Cc: Palmer Dabbelt <palmer at dabbelt dot com>
- Date: Tue, 1 Nov 2016 17:28:37 -0700
- Subject: [PATCH] Build the RISC-V texinfo documentation
- Authentication-results: sourceware.org; auth=none
The RISC-V documentation didn't actually work before: it wasn't even
being built because nothing was included properly. This patch fixes the
syntax errors in the documentation and links everything together so it
builds. I also went through and added a RISC-V section wherever there
was an RX section before.
---
gas/doc/Makefile.am | 1 +
gas/doc/Makefile.in | 1 +
gas/doc/all.texi | 1 +
gas/doc/as.texinfo | 14 ++++++++++++++
gas/doc/c-riscv.texi | 8 ++++----
5 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index 88fa602..54d7ef1 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -81,6 +81,7 @@ CPU_DOCS = \
c-pj.texi \
c-ppc.texi \
c-rl78.texi \
+ c-riscv.texi \
c-rx.texi \
c-s390.texi \
c-score.texi \
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index 5f09b6c..474bd48 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -355,6 +355,7 @@ CPU_DOCS = \
c-pj.texi \
c-ppc.texi \
c-rl78.texi \
+ c-riscv.texi \
c-rx.texi \
c-s390.texi \
c-score.texi \
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index abbca2f..3c25d39 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -63,6 +63,7 @@
@set PJ
@set PPC
@set RL78
+@set RISCV
@set RX
@set S390
@set SCORE
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index b1d94d5..2b00acc 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -511,6 +511,13 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-mint-register=@var{number}}]
[@b{-mgcc-abi}|@b{-mrx-abi}]
@end ifset
+@ifset RISCV
+
+@emph{Target RISC-V options:}
+ [@b{-m32}|@b{-m64}]
+ [@b{-mrvc}]
+ [@b{-mhard-float}|@b{-msoft-float}]
+@end ifset
@ifset S390
@emph{Target s390 options:}
@@ -7592,6 +7599,9 @@ subject, see the hardware manufacturer's manual.
@ifset RL78
* RL78-Dependent:: RL78 Dependent Features
@end ifset
+@ifset RISCV
+* RISC-V-Dependent:: RISC-V Dependent Features
+@end ifset
@ifset RX
* RX-Dependent:: RX Dependent Features
@end ifset
@@ -7819,6 +7829,10 @@ family.
@include c-rl78.texi
@end ifset
+@ifset RISCV
+@include c-riscv.texi
+@end ifset
+
@ifset RX
@include c-rx.texi
@end ifset
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 984b75c..8674ff2 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -15,10 +15,10 @@
@cindex RISC-V support
@menu
-* RISC-V Options:: RISC-V Options
+* RISC-V-Opts:: RISC-V Options
@end menu
-@node RISC-V Options
+@node RISC-V-Opts
@section Options
The following table lists all availiable RISC-V specific options
@@ -40,8 +40,8 @@ Enables the C ISA subset for compressed instructions.
Select the floating-point ABI, hard-float has F registers while soft-float
doesn't.
-@cindex @samp{-march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,}} option, RISC-V
-@item -march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,}
+@cindex @samp{-march=ISA} option, RISC-V
+@item -march=ISA
Select the base isa, as specified by ISA. For example -march=RV32IMA.
@end table
--
2.7.3